LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CHK IS
PORT(DIN,CLK,RST:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END CHK;
ARCHITECTURE one OF CHK IS
TYPE STATES IS (S0,S1,S2,S3,S4);
SIGNAL ST,NST: STATES :=S0;
BEGIN
PROCESS(ST,DIN)
BEGIN
CASE ST IS
WHEN S0=> IF DIN='1' THEN NST<=S1; ELSE NST<=S0;END IF;
WHEN S1=> IF DIN='1' THEN NST<=S2; ELSE NST<=S0;END IF;
WHEN S2=> IF DIN='0' THEN NST<=S3; ELSE NST<=S0;END IF;
WHEN S3=> IF DIN='1' THEN NST<=S4; ELSE NST<=S0;END IF;
WHEN OTHERS=>NST<=S0;
END CASE;
END PROCESS;
PROCESS(CLK,RST)
BEGIN
IF RST='0' THEN ST<=S0;
ELSIF CLK'EVENT AND CLK='1' THEN ST<=NST;
END IF;
END PROCESS;
Y<='1' WHEN ST=S4 ELSE '0';
END ARCHITECTURE one;
