求大神改改vhdl程序，搞半天逻辑还是错误，，为什么高位m1输出一直是零？我所有财富给你们，虽然很少

你已经设置min1<='0'&m1，最高位当然不变。
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
ENTITY tsk1 is
port (
f:in std_logic;
min1,min0: out std_logic_vector(3 downto 0)
);
end tsk1;
architecture behav of tsk1 is
signal w:integer range 0 to 59:=0;
signal m1:std_logic_vector(2 downto 0):="000";
signal m0:std_logic_vector(3 downto 0):="0000";
begin
process(f)
begin
if( f'event and f ='1') then
w <= w + 1;
min1<='0'&m1;
min0<=m0;
if w=59 then
w<=0;
m0<=m0+1;
if m0="1001" then
m0<="0000";
m1<=m1+1;
if m1<="101" then
m1<="000";
end if;
end if;
end if;
end if;
end process;
end behav;