inputA;
inputB;
inputsel;
inputclk;
outputout;
wire[3:0]A;
wire[3:0]B;
wireclk;
wire[2:0]sel;
reg[3:0]out;
always@(posedgeclk)
begin
case(sel)
3'b000:out=A+B;
3'b001:out=A-B;
3'b010:out=A+1;
3'b011:out=A-1;
3'b100:out=A&B;
3'b101:out=A|B;
3'b110:out=~A;
3'b111:out=A^B;
default:out=0;
endcase
end
endmodule
参考我的另外一个回答，
